The present invention relates to a barrel shifter which shifts input data by an amount allocated thereto.
In facsimile signals, original picture images are encoded at a sender side for transmission, and the received codes are decoded at a receiver side. In this processing, the number of white picture elements is counted as a white run length similarly black picture elements a black run length. Then specific codes are allocated to these run lengths depending on the numbers. This code is shortened as its occurrence frequency increases. This remarkably reduces substantial amount of data. Since those codes are variable bit length data which often cause inconvenience in processing, they must be arranged to have a predetermined length.
In JPEG as an international standard for still picture compression, and in MPEG as an international standard for motion picture compression, data are quantized after DCT conversion so as to bind a number of continuation of effective factor that is 0 and effective factors that are not 0 to be encoded to form a code data string. The resultant code data are also variable bit length data which are the same as those used in facsimile transmission. In order to arrange those variable bit length data to have a predetermined length, a barrel shifter is required.
FIG. 6 shows an example of a prior barrel shifter circuit. Its function is explained assuming the maximum bit number of the code data to be input is 16 bit, and the predetermined data length to be output is 16 bit. FIG. 7 shows respective status of a shift register 508, and counters 506 and 507.
At the initial status, the counter 507 is set at 0. Supposing that "1100111" is input as the first code data, a code latch 501 retains this code data. This has a length of 7 bit, thus "7" is retained at a code length latch 502. The output from the code length latch 502 is loaded to the counter 507 through ALU 505 where calculation 32-7=25 is performed, synchronizing with a load signal 551. Therefore, the value of the counter 507 immediately after loading is 25.
The code data retained in the code latch 501 is loaded to a parallel/serial converter 503, synchronizing with the load signal 551. The counter 507 is constructed so as to set a carry signal 552 at "1" when its value becomes 32. It continue to input a clock 553 until the carry signal 552 is set at 1. While the carry signal 552 is set at 1, the shift register 508 retains input data up to 7-th bit from the LSB. The counter 506 indicates the value of 7. This is shown as the status 1 in FIG. 7. Since the value of the counter 506 has not reached 16, the carry signal 554 does not become "1".
Next, supposing that "11100101001" is input as the second code data, the value processed through calculation 32-11=21 is loaded to the counter 507, synchronizing with the load signal 551. The carry signal 554 of the counter 506 is set at "1" by inputting the clock 553. The operation of the counter 507 is suspended by a control circuit 509. This is shown as the status 2 in FIG. 7.
At this time, a latch signal 555 is output to an output latch 510 and data of the shift register 508 are latched. The counter 506 is reset at this stage. This is shown as the status 3 in FIG. 7. Then the counter 507 resumes its operation until the carry signal 552 is set at "1". When the carry signal 552 has become "1", the value of the counter 506 is 2, indicating that the data has been input up to the second bit from the LSB of the shift register 508. This is shown as the status 4 in FIG. 7.
With the above-described structure, for example, processing 11 bit code data requires 11 clocks, thus hindering high-speed processing. Japanese Patent Laid-Open No.57576 (1978) discloses the use of a shift circuit provided with 2 or 1 bit shift function to solve such a problem. This circuit has a relatively simple structure, however, the longer the code data bit length becomes, the more processing time (number of clocks) is required. Accordingly it fails in providing a solution for the high-speed processing. The other Japanese Patent Laid-Open No.25572B (1991) discloses 1 clock shift function. In this case, the circuit size is required to be larger with increase in the bit length of the code to be input, which is not suitable for LSI applications.